`timescale 100us/100us
module gen_tb (
    input           clk_1k,rstn,
    output    reg   q
);

reg clk_1k,rstn;
wire q;
gen gen(
     .q(q)
    ,.clk_1k(clk_1k)
    ,.rstn(rstn)
);

initial begin
   clk_1k = 1'b0;
   rstn = 1'b0;
 end

always  begin
    #20 rstn = 1'b1;
    #20 rstn = 1'b0;
    #20 rstn = 1'b1;
    #50000;
end

always  begin
  #5 clk_1k = ~clk_1k;
end
endmodule //gen_tb